1. Field of the Invention
The present invention relates to control circuits for phase-locked loops (PLLs), and in particular, to control circuits for PLLs having accelerated phase lock times and high sample rates, such as fractional PLLs.
2. Description of the Related Art
Frequency synthesizers are used extensively in wireless applications, such as time division multiplexed and frequency hopping systems, where fast acquisition of phase, or frequency, lock is critical. Also critical is the suppression of spurious signals (e.g., such as those related to the reference signal frequency) and phase noise, particularly for modern digital signal transmission systems.
Channel spacing requirements for such communication systems typically determine the limits for the frequency resolution and loop filter bandwidth associated with such synthesizers. For example, closely spaced channels require the synthesizer frequency resolution to be fine, which, in turn, requires fewer frequency corrections by the loop. While a wider loop filter bandwidth would allow acquisition of phase lock within a shorter time interval, less attenuation would be available for the reference signal frequency sidebands and a higher integrated phase noise would exist during the phase locked condition.
Referring to FIG. 1, a conventional frequency synthesizer 10 using a PLL includes a reference signal source 12, a reference divider circuit 14, a phase detector circuit 16, a charge pump circuit 18, a loop filter circuit 20, a controllable oscillator (e.g., voltage controlled oscillator) 22 and a feedback divider circuit 24, all interconnected substantially as shown. The reference signal source 12, typically a high stability crystal oscillator, provides the reference signal 13 that is frequency-divided by the reference divider circuit 14 to produce a frequency-divided reference signal 15 having a frequency Fr and phase Pr. This reference divider circuit 14 (e.g., a counter) determines the tuning resolution of the overall system 10.
This frequency-divided reference signal 15 is compared with a feedback signal 25 (discussed further below) by the phase detector circuit 16. In accordance with well known conventional techniques, the phases Pr, Pf of these two input signals 15, 25 are compared to one another to produce two control signals 17r, 17f for controlling the charge pump circuit 18. As is well known, depending upon whether the feedback signal 25 is higher or lower in frequency than the frequency-divided reference signal 15, one or the other of the control signals 17r, 17f is active, or asserted, thereby causing the charge pump circuit 18 to source electrical current into or sink electrical current out of the output node 19. The phase detector 16 and charge pump 18 together have an associated gain factor Kxcfx86.
This output charge signal 1.9 provides the input charge to the loop filter circuit 20 which converts such charge into a control voltage 21 for the oscillator circuit 22. In accordance with this control voltage 21, the oscillator circuit 22 generates a radio frequency (RF) output signal 23 having an associated signal frequency Fo and phase Po. This signal 23 is frequency-divided by the feedback divider-circuit 24 (e.g., a counter) to produce the frequency-divided feedback signal 25. The oscillator circuit has a gain factor Kvco/s associated with it.
By comparing the phases Pr, Pf of its input signals, the phase detector 16, in conjunction with the charge pump 18 and loop filter 20, as discussed above, causes the control voltage 21 to the oscillator 22 to be adjusted until the frequency-divided feedback signal 25 has a frequency Ff equal to the frequency Fr of (and phase-aligned with) the frequency-divided reference signal 15. When this condition exists, the PLL 10 is said to be xe2x80x9cphase-lockedxe2x80x9d and the frequency Fo of the oscillator output 23 will be N-times that of the frequency-divided reference signal 15.
Referring to FIG. 2, a well known conventional design for a charge pump circuit 18a includes P-type and N-type metal oxide semiconductor field effect transistors (MOSFETs) connected in a stacked configuration with a current limiting resistor Rdd (as appropriate) between the power supply VDD and circuit ground GND. The charge pump control signals 17r, 17f, turn these transistor N1, P1 on and off for selectively sinking current from or sourcing current to the output terminal 19.
Referring to FIG. 3, a well known conventional design for a passive loop filter circuit 20a includes a shunt capacitor C1 connected in parallel with another shunt circuit having another capacitor C2 and resistor R2 connected in series between the signal terminal 19 and circuit ground GND.
Referring to FIG. 4, the linear control system model for the phase feedback for the synthesizer system 10 of FIG. 1 can be represented as shown. An input summing circuit 16a differentially sums the phases of the frequency-divided reference Pr and feedback Pf signals to produce a phase error Pe which, ideally, will be-driven to zero upon acquisition of phase lock. The open loop gain for this model is the product of the phase comparator gain Kxcfx86, the loop filter gain Z(s) and the oscillator gain Kvco/s, divided by the gain of the feedback counter modulus N in accordance with the following equation:
Pf/Pe=Kxcfx86xc2x7Z(s)xc2x7Kvco/(Nxc2x7s)
So as to minimize phase lock time, the cutoff frequency of the loop filter 20 is selected to be just low enough to suppress the spurious signals related to the frequency-divided reference signal frequency Fr to an acceptable level. One conventional technique for reducing the phase lock time is to dynamically change the cutoff frequency for the loop filter 20 to a higher frequency, thereby reducing the loop response time. Of course, this results in increased spurious signal levels. In order to maintain the same phase margin at this increased loop filter cutoff frequency, other terms in the gain equation above will need to provide some compensation.
One conventional technique has been to reduce the value of the resistor R2 in the loop filter 20 (FIG. 3) during the interval of time used for acquisition of phase lock while also increasing the gain factor Kxcfx86 (by the square of the factor by which the cutoff frequency of the loop filter 20 is increased) of the phase detector and charge pump combination since it can be readily switched in an integrated circuit environment. For example, if the cutoff frequency of the loop filter 20 is doubled, i.e., a factor of 2, the gain factor Kxcfx86, i.e., the available charge pump output current, is increased by a factor of 4 (with the value of the damping resistor reduced by half to maintain a constant phase margin).
While this technique does offer some improvement in the phase lock acquisition interval, such improvement is relatively small. In other words, the improvement in reducing cycle slip using this technique is proportional to the square root of the increase in the gain factor Kxcfx86 (available charge pump output current). It would be desirable to be able to improve cycle slip by a greater degree without needing to rely upon a high charge pump current ratio which can cause spurious signal problems as well as consume significant integrated circuit area.
A control circuit for a PLL with reduced cycle slip during acquisition of phase lock in accordance with the present invention reduces the loop sampling rate while simultaneously increasing the available charge pump current, thereby maintaining a substantially constant loop bandwidth and phase margin during acquisition of phase lock. This significantly reduces cycle slipping, thereby reducing the amount of time needed for acquiring phase lock. Further, this technique is compatible and can be used in conjunction with conventional xe2x80x9cfast lockxe2x80x9d techniques, such as those in which the loop bandwidth in increased. In accordance with the present invention, the improvement in reducing cycle slipping is directly proportional to the increase in current available from the charge pump.
In accordance with one embodiment of the presently claimed invention, a control circuit for a phase-locked loop (PLL) with reduced cycle slip during acquisition of phase lock includes reference division circuitry, feedback division circuitry, phase comparison circuitry and control circuitry. The reference division circuitry, responsive to a reference division control signal, receives and frequency-divides a reference signal with an associated reference signal frequency to provide a frequency-divided reference signal with associated first and second frequency-divided reference signal phases and frequencies corresponding to first and second values of the reference division control signal. The feedback division circuitry, responsive to a feedback division control signal, receives and frequency-divides a feedback signal with an associated feedback signal frequency to provide a frequency-divided feedback signal with associated first and second frequency-divided feedback signal phases and frequencies corresponding to first and second values of the feedback division control signal. The phase comparison circuitry, including output current circuitry and coupled to the reference and feedback division circuitry, compares the frequency-divided reference and feedback signal phases and in response to the phase comparison and a current control signal provides an output state signal and an output current signal with first and second output current signal value ranges corresponding to first and second values of the current control signal. The control circuitry, coupled to the phase comparison circuitry and the reference and feedback division circuitry, responsive to a phase lock control signal and the output state signal, provides the current control signal and the reference and feedback division control signals. A first ratio of the first and second frequency-divided reference signal frequencies, a second ratio of the first and second frequency-divided feedback signal frequencies and a third ratio of the first and second output current signal value ranges are mutually corresponding.
In accordance with another embodiment of the presently claimed invention, a control circuit for a phase-locked loop (PLL) with reduced cycle slip during acquisition of phase lock includes reference divider means, feedback divider means, phase comparator means and controller means. The reference divider means is for responding to a reference division control signal by receiving and frequency-dividing a reference signal with an associated reference signal frequency and providing a frequency-divided reference signal with associated first and second frequency-divided reference signal phases and frequencies corresponding to first and second values of the reference division control signal. The feedback divider means is for responding to a feedback division control signal by receiving and frequency-dividing a feedback signal with an associated feedback signal frequency and providing a frequency-divided feedback signal with associated first and second frequency-divided feedback signal phases and frequencies corresponding to first and second values of the feedback division control signal. The phase comparator means, including output current means, is for comparing the frequency-divided reference and feedback signal phases and responding to the phase comparison and a current control signal by providing an output state signal and an output current signal with first and second output current signal value ranges corresponding to first and second values of the current control signal. The controller means is for responding to a phase lock control signal and the output state signal by providing the current control signal and the reference and feedback division control signals. A first ratio of the first and second frequency-divided reference signal frequencies, a second ratio of the first and second frequency-divided feedback signal frequencies and a third ratio of the first and second output current signal value ranges are mutually corresponding.
In accordance with still another embodiment of the presently claimed invention, a method for controlling a phase-locked loop (PLL) with reduced cycle slip during acquisition of phase lock includes:
receiving and frequency-dividing a reference signal with an associated reference signal frequency and generating a frequency-divided reference signal with associated first and second frequency-divided reference signal phases and frequencies corresponding to first and second values of the reference division control signal;
receiving and frequency-dividing a-feedback signal with an associated feedback signal frequency and generating a frequency-divided feedback signal with associated first and second frequency-divided feedback signal phases and frequencies corresponding to first and second values of the feedback division control signal;
comparing the frequency-divided reference and feedback signal phases and responding to the phase comparison by generating an output current signal with first and second output current signal value ranges corresponding to first and second values of the current control signal; and
controlling the generating of the frequency-divided reference signal, the frequency-divided feedback signal and the output current signal such that a first ratio of the first and second frequency-divided reference signal frequencies, a second ratio of the first and second frequency-divided feedback signal frequencies and a third ratio of the first and second output current signal value ranges are mutually corresponding.